/**
  ******************************************************************************
  * @file    _tc32l010_syscfg.h
  * @author  CHIPAT Application Team
  * @brief   This file contains all the functions prototypes for the WWDG firmware
  *          library.
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XS32L010_SYSCFG_H
#define __XS32L010_SYSCFG_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "tc32l010.h"
#include "tc32l010_rcc.h"

/** @addtogroup XS32L010_StdPeriph_Driver
  * @{
  */

/** @addtogroup SYSCFG
  * @{
  */

/* Exported types ------------------------------------------------------------*/

/** @defgroup SYSCFG_Port_Types SYSCFG Exported Types
  * @{
  */

#define SPINSS_SEL_HIGH           ((uint8_t)0x00)
#define SPINSS_SEL_PA1            ((uint8_t)0x01)
#define SPINSS_SEL_PA2            ((uint8_t)0x02)
#define SPINSS_SEL_PA3            ((uint8_t)0x03)
#define SPINSS_SEL_PB4            ((uint8_t)0x04)
#define SPINSS_SEL_PB5            ((uint8_t)0x05)
#define SPINSS_SEL_PC3            ((uint8_t)0x06)
#define SPINSS_SEL_PC4            ((uint8_t)0x07)
#define SPINSS_SEL_PC5            ((uint8_t)0x08)
#define SPINSS_SEL_PC6            ((uint8_t)0x09)
#define SPINSS_SEL_PC7            ((uint8_t)0x0A)
#define SPINSS_SEL_PD1            ((uint8_t)0x0B)
#define SPINSS_SEL_PD2            ((uint8_t)0x0C)
#define SPINSS_SEL_PD3            ((uint8_t)0x0D)
#define SPINSS_SEL_PD4            ((uint8_t)0x0E)
#define SPINSS_SEL_PD6            ((uint8_t)0x0F)

#define IS_SPINSS_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == SPINSS_SEL_HIGH) || \
                                           ((PORTSOURCE) == SPINSS_SEL_PA1) || \
                                           ((PORTSOURCE) == SPINSS_SEL_PA2) || \
                                           ((PORTSOURCE) == SPINSS_SEL_PA3) || \
                                           ((PORTSOURCE) == SPINSS_SEL_PB4) || \
                                           ((PORTSOURCE) == SPINSS_SEL_PB5) || \
                                           ((PORTSOURCE) == SPINSS_SEL_PC3) || \
                                           ((PORTSOURCE) == SPINSS_SEL_PC4) || \
                                           ((PORTSOURCE) == SPINSS_SEL_PC5) || \
                                           ((PORTSOURCE) == SPINSS_SEL_PC6) || \
                                           ((PORTSOURCE) == SPINSS_SEL_PC7) || \
                                           ((PORTSOURCE) == SPINSS_SEL_PD1) || \
                                           ((PORTSOURCE) == SPINSS_SEL_PD2) || \
                                           ((PORTSOURCE) == SPINSS_SEL_PD3) || \
                                           ((PORTSOURCE) == SPINSS_SEL_PD4) || \
                                           ((PORTSOURCE) == SPINSS_SEL_PD6)) 
/**
  * @}
  */

/** @defgroup SYSCFG_PCA_Pin_sources 
  * @{
  */ 
#define PCA_CAP_SEL_PCACHn                ((uint8_t)0x00)
#define PCA_CAP_SEL_USART0_RXD            ((uint8_t)0x01)
#define PCA_CAP_SEL_USART1_RXD            ((uint8_t)0x02)
#define PCA_CAP_SEL_LPUART_RXD            ((uint8_t)0x03)

#define IS_PCA_CAPn_SEL(SEL)              (((SEL) == PCA_CAP_SEL_PCACHn) || \
                                           ((SEL) == PCA_CAP_SEL_USART0_RXD) || \
                                           ((SEL) == PCA_CAP_SEL_USART1_RXD) || \
                                           ((SEL) == PCA_CAP_SEL_LPUART_RXD))

#define PCA_CAP0                           0
#define PCA_CAP1                           1
#define PCA_CAP2                           2
#define PCA_CAP3                           3
#define PCA_CAP4                           4
#define IS_PCA_CAP_CHN(CHN) (((CHN) >= 0x0) && ((CHN) <= 4))
                                          
/**
  * @}
  */

/** @defgroup SYSCFG_TIM1_Pin_sources 
  * @{
  */ 
#define TIM1_CHxIN_SEL_TIMCHx              ((uint8_t)0x00)
#define TIM1_CHxIN_SEL_USART0_RXD          ((uint8_t)0x01)
#define TIM1_CHxIN_SEL_USART1_RXD          ((uint8_t)0x02)
#define TIM1_CHxIN_SEL_LPUART_RXD          ((uint8_t)0x03)
#define TIM1_CHxIN_SEL_LSI                 ((uint8_t)0x04)

#define IS_TIM1_CH1IN_SEL(SEL)            (((SEL) == TIM1_CHxIN_SEL_TIMCHx) || \
                                           ((SEL) == TIM1_CHxIN_SEL_USART0_RXD) || \
                                           ((SEL) == TIM1_CHxIN_SEL_USART1_RXD) || \
                                           ((SEL) == TIM1_CHxIN_SEL_LPUART_RXD) || \
                                           ((SEL) == TIM1_CHxIN_SEL_LSI))

#define TIM1_CH1IN                         0
#define TIM1_CH2IN                         1
#define TIM1_CH3IN                         2
#define TIM1_CH4IN                         3
#define IS_TIM1_INPUT_CHN(CHN)            (((CHN) >= 0x0) && ((CHN) <= 3))

#define TIM1_ETR_SEL_LOW                   ((uint32_t)0x00000000)
#define TIM1_ETR_SEL_PA1                   ((uint32_t)0x00010000)
#define TIM1_ETR_SEL_PA2                   ((uint32_t)0x00020000)
#define TIM1_ETR_SEL_PA3                   ((uint32_t)0x00030000)
#define TIM1_ETR_SEL_PB4                   ((uint32_t)0x00040000)
#define TIM1_ETR_SEL_PB5                   ((uint32_t)0x00050000)
#define TIM1_ETR_SEL_PC3                   ((uint32_t)0x00060000)
#define TIM1_ETR_SEL_PC4                   ((uint32_t)0x00070000)
#define TIM1_ETR_SEL_PC5                   ((uint32_t)0x00080000)
#define TIM1_ETR_SEL_PC6                   ((uint32_t)0x00090000)
#define TIM1_ETR_SEL_PC7                   ((uint32_t)0x000A0000)
#define TIM1_ETR_SEL_PD1                   ((uint32_t)0x000B0000)
#define TIM1_ETR_SEL_PD2                   ((uint32_t)0x000C0000)
#define TIM1_ETR_SEL_PD3                   ((uint32_t)0x000D0000)
#define TIM1_ETR_SEL_PD4                   ((uint32_t)0x000E0000)
#define TIM1_ETR_SEL_PD6                   ((uint32_t)0x000F0000)


#define IS_TIM1_ETR_SEL(SEL)              (((SEL) == TIM1_ETR_SEL_LOW) || \
                                           ((SEL) == TIM1_ETR_SEL_PA1) || \
                                           ((SEL) == TIM1_ETR_SEL_PA2) || \
                                           ((SEL) == TIM1_ETR_SEL_PA3) || \
                                           ((SEL) == TIM1_ETR_SEL_PB4) || \
                                           ((SEL) == TIM1_ETR_SEL_PB5) || \
                                           ((SEL) == TIM1_ETR_SEL_PC3) || \
                                           ((SEL) == TIM1_ETR_SEL_PC4) || \
                                           ((SEL) == TIM1_ETR_SEL_PC5) || \
                                           ((SEL) == TIM1_ETR_SEL_PC6) || \
                                           ((SEL) == TIM1_ETR_SEL_PC7) || \
                                           ((SEL) == TIM1_ETR_SEL_PD1) || \
                                           ((SEL) == TIM1_ETR_SEL_PD2) || \
                                           ((SEL) == TIM1_ETR_SEL_PD3) || \
                                           ((SEL) == TIM1_ETR_SEL_PD4) || \
                                           ((SEL) == TIM1_ETR_SEL_PD6))

/**
  * @}
  */

/** @defgroup SYSCFG_TIM2_Pin_sources 
  * @{
  */ 
#define TIM2_CHxIN_SEL_TIMCHx              ((uint32_t)0x00000000)
#define TIM2_CHxIN_SEL_USART0_RXD          ((uint32_t)0x00000001)
#define TIM2_CHxIN_SEL_USART1_RXD          ((uint32_t)0x00000002)
#define TIM2_CHxIN_SEL_LPUART_RXD          ((uint32_t)0x00000003)
#define TIM2_CHxIN_SEL_LSI                 ((uint32_t)0x00000004)

#define IS_TIM2_CH1IN_SEL(SEL)            (((SEL) == TIM2_CHxIN_SEL_TIMCHx) || \
                                           ((SEL) == TIM2_CHxIN_SEL_USART0_RXD) || \
                                           ((SEL) == TIM2_CHxIN_SEL_USART1_RXD) || \
                                           ((SEL) == TIM2_CHxIN_SEL_LPUART_RXD) || \
                                           ((SEL) == TIM2_CHxIN_SEL_LSI))

#define TIM2_CH1IN                         0
#define TIM2_CH2IN                         1
#define TIM2_CH3IN                         2
#define TIM2_CH4IN                         3
#define IS_TIM2_INPUT_CHN(CHN)            (((CHN) >= 0x0) && ((CHN) <= 3))


#define TIM2_ETR_SEL_LOW                   ((uint32_t)0x00000000)
#define TIM2_ETR_SEL_PA1                   ((uint32_t)0x00010000)
#define TIM2_ETR_SEL_PA2                   ((uint32_t)0x00020000)
#define TIM2_ETR_SEL_PA3                   ((uint32_t)0x00030000)
#define TIM2_ETR_SEL_PB4                   ((uint32_t)0x00040000)
#define TIM2_ETR_SEL_PB5                   ((uint32_t)0x00050000)
#define TIM2_ETR_SEL_PC3                   ((uint32_t)0x00060000)
#define TIM2_ETR_SEL_PC4                   ((uint32_t)0x00070000)
#define TIM2_ETR_SEL_PC5                   ((uint32_t)0x00080000)
#define TIM2_ETR_SEL_PC6                   ((uint32_t)0x00090000)
#define TIM2_ETR_SEL_PC7                   ((uint32_t)0x000A0000)
#define TIM2_ETR_SEL_PD1                   ((uint32_t)0x000B0000)
#define TIM2_ETR_SEL_PD2                   ((uint32_t)0x000C0000)
#define TIM2_ETR_SEL_PD3                   ((uint32_t)0x000D0000)
#define TIM2_ETR_SEL_PD4                   ((uint32_t)0x000E0000)
#define TIM2_ETR_SEL_PD6                   ((uint32_t)0x000F0000)


#define IS_TIM2_ETR_SEL(SEL)              (((SEL) == TIM2_ETR_SEL_LOW) || \
                                           ((SEL) == TIM2_ETR_SEL_PA1) || \
                                           ((SEL) == TIM2_ETR_SEL_PA2) || \
                                           ((SEL) == TIM2_ETR_SEL_PA3) || \
                                           ((SEL) == TIM2_ETR_SEL_PB4) || \
                                           ((SEL) == TIM2_ETR_SEL_PB5) || \
                                           ((SEL) == TIM2_ETR_SEL_PC3) || \
                                           ((SEL) == TIM2_ETR_SEL_PC4) || \
                                           ((SEL) == TIM2_ETR_SEL_PC5) || \
                                           ((SEL) == TIM2_ETR_SEL_PC6) || \
                                           ((SEL) == TIM2_ETR_SEL_PC7) || \
                                           ((SEL) == TIM2_ETR_SEL_PD1) || \
                                           ((SEL) == TIM2_ETR_SEL_PD2) || \
                                           ((SEL) == TIM2_ETR_SEL_PD3) || \
                                           ((SEL) == TIM2_ETR_SEL_PD4) || \
                                           ((SEL) == TIM2_ETR_SEL_PD6))

/**
  * @}
  */
  
/** @defgroup SYSCFG_Memory_Remap_Config 
  * @{
  */ 
#define SYSCFG_MemoryRemap_Flash                ((uint8_t)0x00)
#define SYSCFG_MemoryRemap_SystemMemory         ((uint8_t)0x01)
#define SYSCFG_MemoryRemap_SRAM                 ((uint8_t)0x03)


#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
                                       ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
                                       ((REMAP) == SYSCFG_MemoryRemap_SRAM))

/**
  * @}
  */


/** @defgroup SYSCFG_Lock_Config 
  * @{
  */ 
#define SYSCFG_Break_Lockup                  SYSCFG_CFGR2_LOCKUP_LOCK       /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */

#define IS_SYSCFG_LOCK_CONFIG(CONFIG) ((CONFIG) == SYSCFG_Break_Lockup)

/**
  * @}
  */
  

/**
  * @}
  */

/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */

/*  Function used to set the SYSCFG configuration to the default reset state **/
void SYSCFG_DeInit(void);

/* SYSCFG configuration functions *********************************************/ 
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
void SYSCFG_PortConfig(uint8_t SPINSS_Sel);
void SYSCFG_PCAConfig(uint8_t Chn, uint8_t CAP_Sel);
void SYSCFG_TIM1ChnConfig(uint8_t Chn, uint8_t ChxIn_Sel);
void SYSCFG_TIM1ETRConfig(uint32_t ETR_Sel);
void SYSCFG_TIM2ChnConfig(uint8_t Chn, uint8_t ChxIn_Sel);
void SYSCFG_TIM2ETRConfig(uint32_t ETR_Sel);

/**
  * @}
  */

#ifdef __cplusplus
}
#endif

#endif /* __XS32F0xx_SYSCFG_H */

/************************ (C) COPYRIGHT CHIPAT *****END OF FILE****/
